1. Field of the Invention
The embodiments disclosed herein relate to modeling parasitic resistances in semiconductor devices and, more particularly, to embodiments of a method, a system and a program storage device for modeling the total gate resistance of a multi-gate field effect transistor (MUGFET), which incorporates multiple semiconductor fins.
2. Description of the Related Art
Gate resistance of a field effect transistor (FET) is a relatively large parasitic resistance that will impact the performance of very large scale integration (VLSI) circuits, such as ring oscillators, logic gates (e.g., NAND gates, NOR gates, etc.), etc. Specifically, this parasitic resistance is associated with the flow of gate current (including both alternating current (AC) and gate leakage direct current ((DC)) from the FET channel region through the FET gate structure and the higher the gate resistance, the slower the switching speed of the FET. Thus, during FET design, accurate modeling of gate resistance is very important. Various techniques are well known in the art for modeling gate resistance for conventional planar FETs. Recently, however, multi-gate non-planar field effect transistors (MUGFETs) (e.g., dual-gate non-planar FETs, also referred to herein as fin-type FETs (FINFETs), and tri-gate non-planar FETs) and, particularly, multi-fin MUGFETs have been developed to provide reduced-size field effect transistors, while simultaneously providing enhanced control in short channel effects (SCE) and reducing drain induced barrier lowering (DIBL) significantly. Unfortunately, for such MUGFETs, the prior art gate resistance modeling techniques do not provide accurate results because of the complex three-dimensional geometries involved. Therefore, there is a need in the art for technique that can be used to more accurately model gate resistance of multi-fin MUGFETs.